Elaheh (Eli) Bozorgzadeh is one of Iran’s and also world’s most influential senior research scientist at the Center for Embedded Computer Systems (CECS) in California, Los Angeles.

She’s also research scientist at California Institute for Telecommunication and Information Technology (Calit2).

Elaheh Bozorgzadeh is one of the youngest Associated professors at University of California Los Angeles. Professor Bozorgzadeh is the Director of Reconfigurable Computing Lab at UCLA, at Computer Science Department.

Education

• 1998 at age 19 – B.S. in Electrical Engineering – Sharif University of Technology, Tehran-Iran.
• 2000 at age 21 – M.S. in Electrical and Computer Engineering – Northwestern University, Evanston.
• 2003 at age 24 – Ph.D. in Computer Science – University of California Los Angeles, in Irvine.
• 2005 at age 26 – Assistant Professor in Computer science – University of California, Los Angeles.
• 2007 at age 28 – Associated Professor in Computer Science – University of California Los Angeles.

Real-Time Developing Efficient Objects for Embedded Systems is an introduction to object-oriented analysis and design for hard real-time systems and provides a notation for capturing and communicating object structure and behavior.

An embedded system is a computer system designed to perform one or a few dedicated functions often with real-time computing constraints. It is embedded  as part of a complete device often including hardware and mechanical parts.

By contrast, a general-purpose computer, such as a personal computer (PC), is designed to be flexible and to meet a wide range of end-user needs. Embedded systems control many devices in common use today.

Professor Elaheh Bozorgzadeh is expert at System Synthesis for Self-adaptive Reconfigurable Embedded Systems. Embedded systems are controlled by one or more main processing cores that is typically either a microcontroller or a digital signal processor (DSP).

The key characteristic is however being dedicated to handle a particular task, which may require very powerful processors. For example, air traffic control systems may usefully be viewed as embedded, even though they involve mainframe computers and dedicated regional and national networks between airports and radar sites. (Each radar probably includes one or more embedded systems of its own.)In order to abstract away the design complexity, each design is decomposed into a set of sub-designs and hierarchical design process is applied.

Along with timing, there are other constraints such as size, power dissipation, etc. The sub-designs along the critical paths are the most constrained components during the optimization process in CAD flow. However, timing constraint is more relaxed on the other parts of the design. Bozorgzadeh is also expert science of Physically-aware Architectural Synthesis and layout planning for Embedded Systems and Director of Reconfigurable Computing Lab at University of California at Irvine.

Research Interests

• System Synthesis for Self-adaptive Reconfigurable Embedded Systems
• Physically-aware Architectural Synthesis and layout planning for Embedded Systems
• MAC-layer-in-loop seamless multiprotocol communication support on reconfigurable architectures
• Early physical planning for rapid timing closure (Timing budget management)

Awards

• NSF CAREER Award, “CAREER:System Synthesis for Self-adaptive Reconfigurable Embedded Systems”, 2009.
• NSF CAREER Award, 2008
• Best paper award, IEEE International Conference in Field Programmable Logic and Applications (FPL), 2006.
• Best paper award, 2006 IEEE International Conference on Field Programmable Logic and Applications (FPL’06)
• Best paper award nominee, ACM/IEEE Design Automation Conference (DAC’05), 2005
• UCI Faculty Career Development Award for 2006-07
• Best Poster Presentation Award, Graduate Student Poster Sessions, Research Review, Computer Science Department, UCLA, 2001.
• Best Poster Award, Graduate Student Poster Session, 2000 ECE Advisory Board Meeting, ECE Department, Northwestern University.

Scientific journal papper
J18- L. Singhal, S. Oh, and E. Bozorgzadeh, “Statistical Power Profile Correlation for Realistic Thermal-aware Floorplanning”, under minor revision for publication in ACM Transactions on Design Automation of Embedded Systems (TODAES).

J17- S. Banerjee, E. Bozorgzadeh, J Noguera, and N. Dutt, “Bandwidth Management in Application Mapping for Dynamically Reconfigurable Architectures”, under minor revision for publication in ACM Transactions on Reconfigurable Technology and Systems (TRETS).

J16- S. Banerjee, E. Bozorgzadeh, and N. Dutt, “Exploiting application data-parallelism on dynamically reconfigurable architectures: placement and architectural considerations “, to appear in IEEE Transactions on VLSI (TVLSI).

J15- S. Oh, T. Kim, J. Cho and E. Bozorgzadeh, “Speculative Loop-Pipelining in Binary Translation for Hardware Acceleration”, IEEE Transactions on CAD (TCAD), pp. 409- 422, No. 3, Vol. 27, 2008.

J14- L. Singhal and E. Bozorgzadeh, “Multi-layer Floorplanning for Reconfigurable Designs”, in IET Computers & Digital Techniques, pp. 276-294, No. 1, Vol. 4, 2007.

J13-L. Singhal, E. Bozorgzadeh, and D. Eppstein, “Interconnect Criticality Driven Delay Relaxation”, in IEEE Transactions on CAD (TCAD),pp.1803-1817, ,No. 10, Vol. 26, 2007.

J12- S. Banerjee, E. Bozorgzadeh, N. Dutt, “Integrating physical constraints in HW-SW partitioning for architectures with partial dynamic reconfiguration”, in IEEE Transactions on VLSI (TVLSI), Vol 14 (11), pp 1189-1202, Nov 2006.

J11- S. Ghiasi, E. Bozorgzadeh, P. Huang, R. Jafari, and M. Sarrafzadeh, “A Unified Theory of Timing Budget Management”, in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol. 25, No. 11, pp. 2364-2375, November 2006.

J10- S. Pasricha, N. Dutt, , E. Bozorgzadeh, M. Ben-Romdhane, ” FABSYN: Floorplan-Aware Bus Architecture Synthesis”, in IEEE Transactions on VLSI (TVLSI), pp. 241-253 ,Vol. 14, No. 3, 2006.

J9- G. Wang, S. Sivaswamy, C. Ababei, K. Bazargan, R. Kastner, and E. Bozorgzadeh, “Statistical Analysis and Design of HARP FPGAs”, in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), pp. 2088-2102, Vol. 25, No. 10, 2006.

J8- S. Ghiasi, K. Nguyen, E. Bozorgzadeh, M. Sarrafzadeh, “Efficient Timing Budget Management for Accuracy Improvement in a Collaborative Object Tracking System”, in Journal of VLSI Signal Processing for Signal Processing and Video Technology, 42(1), pp. 43-55.
2006.

J7- S. Ogrenci Memik, R. Kastner, E. Bozorgzadeh, and M. Sarrafzadeh, “A Scheduling Algorithm for Optimization and Early Planning in High level Synthesis”, ACM Transactions on Design Automation of Electronic Systems (TODAES), Vol. 10, No. 1, pp. 33–57, January 2005.

J6- E. Bozorgzadeh, S. Ghiasi, A. Takahashi , and M. Sarrafzadeh, “Optimal Integer Delay Budget Assignment on Directed Acyclic Graphs”, in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol. 23, No. 7, pp. 1184- 1199 , August 2004.

J5- E. Bozrgzadeh, S. Ogrenci Memik, X. Yang, and M. Sarrafzadeh, “Routability-driven Packing : Metrics and Algorithms for Cluster-based FPGAs”, in Journal of Circuits, Systems, and Computers (JCSC), Vol. 13, No. 1, pp. 77-100, Feb. 2004.

J4- E. Bozorgzadeh, R. Kastner, and Majid Sarrafzadeh, “Creating and Exploiting Flexibility in Rectilinear Steiner Trees”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), pp.605-615, Vol. 22, No. 5, May 2003.

J3- R. Kastner, Adam Kaplan, S. Ogrenci Memik, E. Bozorgzadeh, “Instruction Generation for Hybrid Reconfigurable Systems”, ACM Transactions on Design Automation of Embedded Systems (TODAES), pp. 605-627, Vol.7, No. 4, October 2002.

J2- C. Chen, E. Bozorgzadeh, A. Srivastava, and Majid Sarrafzadeh, “Budget Management with Applications”, Algorithmica, Vol. 34, No. 3, pp. 261-275, July 2002.

J1- R. Kastner, E. Bozorgzadeh, and M. Sarrafzadeh, “Pattern Routing: Use and Theory for Increasing Predictability and Avoiding Coupling”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), pp. 777-790, vol. 21, No. 7, July 2002.